STMicroelectronics ST25R3916B-AQWT New NFC Reader Speeds Design of Payment and Consumer Applications

STMicroelectronics ST25R3916B-AQWT New NFC Reader Speeds Design of Payment and Consumer Applications
Post Date:2022-07-27,STMicroelectronics

STMicroelectronics ST25R3916B-AQWT New NFC Reader Speeds Design of Payment and Consumer Applications

STMicroelectronics' ST25R3916B-AQWT reader chip has high output power, high energy efficiency, and competitive price. It supports four modes of NFC initiator, target device, reading and card emulation. Target applications include contactless payment, device pairing, Wireless charging, brand protection, and other industrial and consumer applications.

The new device introduces a more flexible active waveform shaping improvement that simplifies the RF output adjustment process and facilitates optimization of overshoot and undershoot issues. The RF adjustment operation is very easy, first modify the register settings on the supported GUI software, and then use the oscilloscope for quick verification. This technology simplifies EMVCo 3.1a and NFC Forum CR13 specification certification without having to deal with antenna matching issues.

New NFC Reader from STMicroelectronics Speeds Design of Payment and Consumer Applications

The ST25R3916B and ST25R3917B provide up to 1.6W of RF output power and can drive antennas directly and efficiently. Dynamic power output scaling technology allows designers to control radiated power within the upper and lower limits defined by the EMVCo and NFC Forum specifications.

ST25R3916B/17B integrates high noise immunity input structure and STMicroelectronics proprietary Noise Suppression Receiver (NSR). Both devices have strong immunity to radiated noise and conducted noise.

The power supply voltage range of ST25R3916B/17B chip is 2.4V - 5.5V, and the operating temperature range is -40°C - 105°C. The minimum operating voltage of the peripheral I/O circuit is 1.65V.
The new products are available in a 32-pin VFQFPN 5mm x 5mm x 1mm package and a 36-bump wafer-level chip-level package (WLCSP).

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